Researchers have, for the first time, added two‑terminal ferroelectric memory cells directly to the back‑end‑of‑line (BEOL) of intact 180‑nm CMOS wafers. A tungsten‑titanium‑nitride–oxygen‑rich layer was sandwiched with a five‑cycle HfO₂/ZrO₂ multilayer and a 2‑nm WOₓ spacer between molybdenum and silicon dioxide. Rapid thermal annealing at 450 °C or 500 °C crystallized the hafnia ferroelectric. Devices could be written with voltages below 1.8 V and show cycle‑to‑cycle variation under 3 %. After 1000 writes, the conductance range grew three‑fold and the variability dropped from 5 % to 1.5 %. The devices retain‐state drift is 7–9 % over two hours, consistent with Merz‑law‑like domain switching. The 500 °C process improves linearity (peak slope < 3) but narrows the usable write window to 2.4 V and leaves a –0.1 V offset, limiting single‑step operation. Neural‑network simulations using analog stochastic gradient descent predict 82 % MNIST accuracy with the 500 °C chip versus 69 % for the 450 °C variant, showing how modest processing changes affect system performance.